1. Field of the Invention
The present invention relates to a design of a system LSI (Large Scale Integration), and more particularly, to a circuit design device, a circuit design program, and a circuit design method for stopping clock supply.
2. Description of Related Art
Up to now, clock supply to an entire LSI is carried out in a unified way, and a circuit for stopping clock supply (hereinafter, referred to as “clock supply stopping circuit”) is manually inserted into the LSI. In recent years, with an increase in scale of the LSI, the conventional LSI is treated as a macro block serving as a single component. For this reason, it is necessary for the clock supply stopping circuit, which is inserted into the LSI, to control a large number of macro blocks. Thus, the clock supply stopping circuit has become more diversified and complicated.
Meanwhile, there is known a technique for inserting the clock supply stopping circuit into a flip-flop (hereinafter, referred to as “F/F”) which does not operate in an LSI. A period in which each F/F does not operate is manually extracted, and based on a result of the extraction, the clock supply stopping circuit is inserted. The insertion of the clock supply stopping circuit is time consuming. Further, in the above-mentioned method of inserting the clock supply stopping circuit, the probability of an error occurring in the extraction and insertion of the clock supply stopping circuit is high. As a result, there arises a problem in that a development period is prolonged and costs thereof are increased.
To solve the above-mentioned problem, it is necessary to provide a method of automatically inserting the clock supply stopping circuit, and a new circuit configuration therefor. For example, relevant techniques as described below are disclosed.
For example, Japanese Unexamined Patent Application Publication No. 2003-330988 discloses a logic circuit design method including the steps of: detecting, from a hardware description, a register forming a state machine and a register operating only when the state machine is in a state other than an idle state; and generating a gated clock supply circuit for supplying a gated clock to the detected registers, to reflect the gated clock supply circuit in the hardware description, and a device therefor. This is a method of inserting the clock supply stopping circuit for stopping clock supply when the state machine is in the idle state.
FIG. 17 is a schematic diagram showing an embodiment of the logic circuit design device as disclosed in Japanese Unexamined Patent Application Publication No. 2003-330988. The logic circuit design device shown in FIG. 17 includes: a unit 10p for inputting conditions for detecting registers; a unit 20p for detecting a register forming a state machine, from a hardware description (HDL source); a unit 30p for detecting the idle state of the state machine, from the HDL source; a unit 40p for detecting a register operating only when the state machine is in a state other than the idle state, from the HDL source; a unit 50p for generating a gated clock supply circuit for supplying a gated clock to the detected registers; and a unit 60p for generating a hardware description reflecting the generated gated clock supply circuit.
FIG. 18 is a circuit diagram showing the gated clock supply circuit generated by the logic circuit design device shown in FIG. 17. As shown in FIG. 18, a circuit block 1 (idle state determination) 70p detects the idle state of the state machine to generate an enable signal IDL_EN for the clock supply stopping circuit. A circuit block 2 (FF) 80p and a circuit block 3 (AND) 90p enable automatic insertion of the clock supply stopping circuit only into a circuit block 4 (CURRENT_STATE register C) 100p forming the state machine.
Japanese Unexamined Patent Application Publication No. 2002-92065 discloses a circuit design method and a circuit design device for changing a first F/F (flip-flop), in which a content of an enable signal in an enable state is updated in synchronization with a clock signal, into a second F/F in which the clock signal is gated based on the enable signal. This is a method of inserting the clock supply stopping circuit when the F/F is in a disable state.
FIG. 19 is a diagram showing the configuration of the circuit design device as disclosed in Japanese Unexamined Patent Application Publication No. 2002-92065. The circuit design device shown in FIG. 19 implements a circuit design method as described below. The circuit design method includes: a step (2p) of obtaining an operation condition of an F/F by analyzing a hardware description, to extract an enable signal; a step (3p) of changing the hardware description into a hardware description indicating a correspondence relation between the enable signal and the F/F; a step (5p) of inputting the changed RTL description and test vectors to simulate a circuit; a step of obtaining an active ratio that is a ratio at which the enable state is obtained from the simulation result; a step (7p) of changing the F/F into a gated clocked F/F based on the active ratio; and a step (8p) of outputting the result as a hardware description.
FIG. 20 is a diagram showing the configuration obtained by forming a gated clock using the logic circuit design device shown in FIG. 19. Referring to FIG. 20, a description is given of a logic circuit represented in the hardware description obtained after inserting the clock supply stopping circuit generated using the technique disclosed in Japanese Unexamined Patent Application Publication No. 2002-92065. In FIG. 20, “en” representing a signal corresponding to an input of a latch circuit 103p becomes High when an F/F 102p is operating and becomes Low when the F/F 102p is not operating. The latch circuit 103p and an AND gate 104p enable automatic insertion of the clock supply stopping circuit only into the F/F 102p with an enable. Further, as a related art, there is disclosed the following clock signal control system (see Japanese Unexamined Patent Application Publication No. 57-108911). That is, in an electronic computer incorporating a group of flip-flop circuits having an extremely high propagation rate, to prevent an output from the flip-flop circuits from being unstable when a clock signal and a reset signal are simultaneously input to the flip-flop circuits, a reset operation is performed in a state where the input of the clock signal is temporarily stopped, to thereby bring the group of flip-flop circuits into a complete reset state.
However, the technique as disclosed in Japanese Unexamined Patent Application Publication No. 2003-330988 relates to the method of inserting the clock supply stopping circuit only into the F/F forming the state machine. Further, the technique as disclosed in Japanese Unexamined Patent Application Publication No. 2002-92065 relates to the method of inserting the clock supply stopping circuit only into the F/F with an enable. Accordingly, in the techniques as disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-330988 and 2002-92065, it is impossible to insert the clock supply stopping circuit into F/Fs other than the F/F forming the state machine and the F/F with an enable.
An F/F is also used as, for example, a circuit for holding a set value or a circuit for delaying data by several clocks. Accordingly, the F/F is not limited to an F/F used as a circuit forming a state machine and an F/F with an enable. In various types of circuits, F/Fs that do not operate in a reset state are used in many cases. Thus, in the techniques as disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-330988 and 2002-92065, there are a large number of F/Fs that are not extracted as the F/Fs into which the clock supply stopping circuit is inserted. The F/Fs that cannot be extracted according to the techniques as disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-330988 and 2002-92065 correspond to the F/Fs that do not operate in the reset state.
As described above, in the conventional techniques, it is impossible to automatically insert the clock supply stopping circuit into F/Fs receiving a prescribed control signal.